The present invention relates to a new and improved construction of apparatus for controlling the access of microprocessors or processors at a data line.
Generally speaking, the arrangement of the present development is of the type wherein the processors are connected by means of input-output interface components at the data line and each input-output interface component has an input which reads an access requirement or requisition of a processor.
With such type apparatuses it is possible to accomplish by means of standardized commercially available input-output interface components data transfer to a data line between a digital computer and an external component or unit, for instance a teleprinter through the use of serial transmission techniques. Before the data transfer there is clarified, by means of a sequence of control signals, the transmitting and receiving preparedness between the individual terminals. However, if a data exchange is to be accomplished between a number of computer systems or processors, as the case may be, connected with a common data line or between such computer systems or processors and with external components connected with the common data line, then problems arise particularly when encountering simultaneous access to the data line. These problems cannot be readily resolved through the use of standardized input and output components.
With an apparatus of the type disclosed in the German Patent Publication No. 2,824,557 which serves for the direct coupling of a plurality of microprocessors to a common system bus there is proposed a solution to the existing problem. In that prior art system the microprocessors which possess a HOLD-input and a HOLDA-output are provided with a logic device by means of which there can be controlled the access to the system bus. Before the access is released there must be accomplished a bus-requisition or demand cycle in the form of a signal sequence which essentially consists of a requisition or demand signal BUSREQ at a processor which functions as a master and a receipt signal HOLDA of such master at the requistioner or demander. Only when there is present a receipt is it possible for the requisitioner or demander to occupy the bus for one or a number of access operations. In order to accomplish the bus requisition cycle the microprocessors are connected together in accordance with the master-slave principle such that the requisition or demand outputs BUSREQ of the slave processors are coupled by means of an OR-gate with the HOLD-input of the master processor and its receipt output HOLDA is coupled with a receipt input BPRI of the next following slave processor. The slave processors are mutually coupled with one another in such a fashion that in each instance a receipt output BPRO of a preceding slave processor is connected with a receipt input BPRI of a subsequent slave processor.
With this equipment there is determined the priority of the individual microprocessors, so that with simultaneous access of a plurality of microprocessor it is possible in each case for that processor to have access to the bus which is situated closest to the master processor. However, the drawbacks of such state-of-the-art equipment reside in the fact that in addition to the data and control lines of the system bus there are further required additional lines for the accomplishment of the bus-requisition or demand cycle, and with increasing number of microprocessors there also increase the number of requisition or demand lines BUSREQ. What is also disadvantageous with this equipment is that with increasing number of processors the bus allocation becomes much too time-consuming, since the individual processors, during the receipt switching operations, must be sampled in timewise succession in order to ascertain which one of the processors is the requisitioner or demander.